In connection with an increasing reduction in the weight, thickness, and size of electronic equipment, every effort has been made to reduce the sizes of semiconductor elements, to increase the degree of integration, and to improve high-density packaging techniques for semiconductor packages.
For packaging of semiconductor elements such as IC chips, interconnection of a wiring board and a semiconductor element in a package is carried out by wire bonding using gold wires or the like or flip chip interconnection using solder balls or the like.
The wire bonding has the advantage of allowing packaging to be inexpensively achieved if the semiconductor element involves a small number of connection pads. However, wire diameter needs to be reduced with increasing number and decreasing pitch of connection pads. This may disadvantageously lead to inappropriate assembly such as wire breakage and thus reduced manufacturing yield. Furthermore, with the wire bonding, the connection paths between terminals of the semiconductor element and terminals of the wiring board need to have a certain length. This may disadvantageously degrade high-speed transmission characteristics.
The flip chip interconnection enables high-speed signal transmission due to the use of a connection path shorter than in the case of the wire bonding, between the semiconductor element and the wiring board. Furthermore, the flip chip interconnection allows terminals to be provided not only around but also all over a circuit surface of the semiconductor element, enabling an increase in the number of connection terminals. However, the increased number and reduced pitch of connection pads on the semiconductor element reduces the size of solder bumps, disadvantageously leading to reduced connection strength and the increased likelihood of inappropriate connections such as cracks.
In recent years, as a high-density packaging technique for facilitating a further increase in the density of semiconductor elements and further improvement of functions of the semiconductor elements, a packaging technique for building a semiconductor element in a wiring substrate, what is called, a semiconductor element build-in technique, has been proposed. This technique has the advantages of, for example, reducing the thickness and cost of the package, allowing high frequencies to be dealt with, enabling connections to be established with reduced stress, and improving electromigration characteristics.
For example, Patent Literature 1 discloses a ball grid array package including an IC chip fixed on a metal heat sink and buried in an insulating layer, wiring conductors connected directly to packaging pads of the IC chip, externally formed BGA packaging pads electrically connected to the wiring conductors, and BGA solder bumps joined to the BGA packaging pads.
Patent Literature 2 discloses a semiconductor device including a semiconductor chip size package (CSP) with a semiconductor chip, rewiring on the semiconductor chip, a sealing film that covers the rewiring, and columnar electrodes on the rewiring; a frame-like burying material provided on sides of the semiconductor chip size package, a sealing film provided between the semiconductor chip size package and the frame-like burying material, an insulating film covering the semiconductor chip size package, and upper layer-side rewiring provided on the insulating film and connected to the columnar electrodes, wherein the semiconductor chip size package and the frame-like burying material are provided on a base plate.
On the other hand, Patent Literature 3 discloses, as a semiconductor chip for mounting on a packaging board, a semiconductor device including a micro wiring structure portion in which a first wiring layer and a first insulating layer are alternately stacked on a semiconductor substrate, a first macro wiring structure portion in which a second wiring layer and a second insulating layer are alternately stacked on the micro wiring structure portion, and a second macro-wiring structure portion in which a third wiring layer and the second insulating layer are alternately stacked on the first macro wiring structure portion, wherein each of the second and third insulating layers is thicker than the first insulating layer, a modulus of elasticity of the third insulating layer at 25° C. is equal to or lower than a modulus of elasticity of the second insulating layer at 25° C., and each of the second and third wiring layers is at least twice as thick as the first wiring layer. Patent Literature 3 discloses that such a semiconductor device can reduce stress generated after the semiconductor device is mounted on a packaging board.